To increase the degree of integration and the capacity of a NAND flash memory, the design rule needs to be smaller. To reduce the design rule, it is necessary to more finely pattern interconnection patterns and the like. Implementing finer patterning of interconnection patterns and the like requires a very sophisticated processing technique. As a result, reduction of the design rule is difficult.
There has recently been proposed a nonvolatile semiconductor memory in which memory cells are three-dimensionally arranged to achieve a higher degree of memory integration.
In this nonvolatile semiconductor memory, stacked active areas are formed by batch processing, and gate contacts are also formed at once. Stacked memory strings are selected at once by a layer select transistor. This structure enables to reduce the chip area and increase the degree of memory integration. Since the stacked structure can be formed by batch processing, the manufacturing cost can largely be suppressed.
Even in this structure, however, a layer select transistor and a contact plug are formed for each layer of memory strings. For this reason, the area to form them is necessary. The number of memory strings consequently increases as the number of stacked layers increases. In addition, it is difficult to form an interconnection leader from each of the stacked memory strings. Furthermore, forming interconnection leaders leads to an increase in the number of interconnections and the circuit area, resulting in few merits in forming the stacked structure.
There is no disclosure of a nonvolatile semiconductor memory structure capable of solving these problems at the moment.